TSMC admits it can't produce enough AI chips as demand outpaces supply

In context: Chip-on-wafer-on-substrate is simply a packaging exertion that integrates aggregate chips into a azygous package to create high-performance computing and AI components. The section is presently dominated by TSMC, though different Taiwanese firms specified arsenic UMC, ASE Technology Holding, and Powertech Technology are besides entering nan market.

With AI showing nary signs of slowing, TSMC will beryllium ramping up its precocious spot packaging capabilities complete nan adjacent fewer years. During its caller net telephone connected October 17, nan chipmaker revealed that its accumulation capacity for CoWoS packaging exertion is group to double year-over-year successful some 2024 and 2025.

However, request is truthful beardown that moreover pinch this accelerated description , nan institution suggests it still can't nutrient packages accelerated capable for its customers.

Currently, precocious packaging accounts for only astir 7 to 9 percent of TSMC's full revenue, but it is simply a fast-growing conception that is expected to outpace nan company's wide maturation complete nan adjacent 5 years. While gross margins are somewhat little than TSMC's average, they are steadily improving arsenic accumulation measurement increases.

Originally, nan manufacture rumor mill expected TSMC's CoWoS capacity description to commencement leveling disconnected by 2026. Early projections had nan company's monthly packaging measurement topping retired astir 100,000 to 120,000 wafers that year. But, astonishment – AI's request keeps growing.

With awesome AI players relentlessly driving demand for cutting-edge chips pinch precocious packaging, TSMC has returned to its instrumentality suppliers to scheme for moreover greater CoWoS capacity successful 2026, according to nan report.

These suppliers apt see companies for illustration GPTC and Scientech, cardinal providers of bedewed process equipment, specified arsenic automated bedewed benches and azygous wafer rotation processors, which TSMC relies on. Scientech, successful particular, appears to person a beardown grip connected CoWoS instrumentality orders astatine nan moment.

These suppliers could soon beryllium printing rate arsenic nan study suggests TSMC could scope an astonishing 140,000 to 150,000 packaged wafers per period by 2026.

To put that successful perspective, by nan extremity of this year, nan institution expects its CoWoS capacity to scope astir 35,000 to 40,000 wafers per month. In 2025, that fig is expected to surge to astir 80,000 wafers.

Beyond ramping up production, nan chipmaker reportedly plans to switch from accepted information wafers to rectangular substrates to summation nan number of chips that tin beryllium placed connected each wafer.